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Features
* Fast Read Access Time - 70 ns * Low Power CMOS Operation
- 100 A Max Standby - 30 mA Max Active at 5 MHz JEDEC Standard Packages - 32-lead PDIP - 32-lead PLCC - 32-lead TSOP 5V 10% Supply High Reliability CMOS Technology - 2000V ESD Protection - 200 mA Latchup Immunity Rapid Programming Algorithm - 100 s/Byte (Typical) CMOS and TTL Compatible Inputs and Outputs Industrial Temperature Range Green (Pb/Halide-free) Packaging Option
*
* *
* * * *
4-Megabit (512K x 8) OTP EPROM AT27C040
1. Description
The AT27C040 chip is a low-power, high-performance, 4,194,304-bit one-time programmable read-only memory (OTP EPROM) organized as 512K by 8 bits. The AT27C040 requires only one 5V power supply in normal read mode operation. Any byte can be accessed in less than 70 ns, eliminating the need for speed reducing WAIT states on high-performance microprocessor systems. Atmel's scaled CMOS technology provides low active power consumption, and fast programming. Power consumption is typically 8 mA in active mode and less than 10 A in standby mode. The AT27C040 is available in a choice of industry-standard JEDEC-approved onetime programmable (OTP) plastic PDIP, PLCC and TSOP packages. The device features two-line control (CE, OE) to eliminate bus contention in high-speed systems. Atmel's AT27C040 has additional features to ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 s/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry-standard programming equipment to select the proper programming algorithms and voltages.
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2. Pin Configurations
Pin Name A0 - A18 O0 - O7 CE OE Function Addresses Outputs Chip Enable Output Enable
2.1
32-lead PDIP Top View
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A18 A17 A14 A13 A8 A9 A11 OE A10 CE 07 06 05 04 03
2.3
32-lead PLCC Top View
A12 A15 A16 VPP VCC A18 A17
2.2
32-lead TSOP Top View
A11 A9 A8 A13 A14 A17 A18 VCC VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE 07 06 05 04 03 GND 02 01 O0 A0 A1 A2 A3
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01 02 GND 03 04 05 06
14 15 16 17 18 19 20
A7 A6 A5 A4 A3 A2 A1 A0 O0
5 6 7 8 9 10 11 12 13
4 3 2 1 32 31 30
29 28 27 26 25 24 23 22 21
A14 A13 A8 A9 A11 OE A10 CE 07
AT27C040
3. Switching Considerations
Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 F high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 F bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array.
4. Block Diagram
5. Absolute Maximum Ratings*
Temperature Under Bias................................ -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground ............................................-2.0V to +7.0V Voltage on A9 with Respect to Ground .........................................-2.0V to +14.0V VPP Supply Voltage with Respect to Ground ..........................................-2.0V to +14.0V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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6. Operating Modes
Mode/Pin Read Output Disable Standby Rapid Program PGM Verify PGM Inhibit Product Identification(4) Notes: 1. X can be VIL or VIH. 2. Refer to Programming Characteristics 3. VH = 12.0 0.5V. 4. Two identifier bytes may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled low (VIL) to select the Manufacturer's Identification byte and high (VIH) to select the Device Code byte.
(2)
CE VIL X VIH VIL X VIH VIL
OE VIL VIH X VIH VIL VIH VIL
Ai Ai X X Ai Ai X A9 = VH A0 = VIH or VIL A1 - A18 = VIL
(3)
VPP X X X VPP VPP VPP X
(1)
Outputs DOUT High Z High Z DIN DOUT High Z Identification Code
7. DC and AC Operating Conditions for Read Operation
AT27C040-70 Industrial Operating Temperature (Case) VCC Power Supply -40C - 85C 5V 10% AT27C040-90 -40C - 85C 5V 10%
8. DC and Operating Characteristics for Read Operation
Symbol ILI ILO IPP1 ISB ICC VIL VIH VOL VOH Notes:
(2)
Parameter Input Load Current Output Leakage Current VPP(1) Read/Standby Current
Condition VIN = 0V to VCC VOUT = 0V to VCC VPP = VCC ISB1 (CMOS), CE = VCC 0.3V ISB2 (TTL), CE = 2.0 to VCC + 0.5V f = 5 MHz, IOUT = 0 mA, CE = VIL
Min
Max 1 5 10 100 1 30
Units A A A A mA mA V V V V
VCC1(1) Standby Current VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
-0.6 2.0 IOL = 2.1 mA IOH = -400 A 2.4
0.8 VCC + 0.5 0.4
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP.
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AT27C040
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AT27C040
9. AC Characteristics for Read Operation
AT27C040 -70 Symbol tACC(1) tCE(1) tOE(1) tDF(1) tOH Note: Parameter Address to Output Delay CE to Output Delay OE to Output Delay Condition CE = OE = VIL OE = VIL CE = VIL Min Max 70 70 30 20 0 0 Min -90 Max 90 90 35 20 Units ns ns ns ns ns
OE or CE High to Output Float, Whichever Occurred First Output Hold from Address, CE or OE, Whichever Occurred First 1. See AC Waveforms for Read Operation
10. AC Waveforms for Read Operation(1)
Notes:
1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE. 3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC. 4. This parameter is only sampled and is not 100% tested. 5. Output float is defined as the point when data is no longer driven.
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11. Input Test Waveforms and Measurement Levels
12. Output Test Load
1.3V (1N914) OUTPUT PIN 3.3K
CL
13. Pin Capacitance
f = 1 MHz, T = 25 C (1)
Symbol CIN COUT Note: Typ 4 8 Max 8 12 Units pF pF Conditions VIN = 0V VOUT = 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
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AT27C040
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AT27C040
14. Programming Waveforms(1)
Notes:
1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH. 2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer. 3. When programming the AT27C040 a 0.1 F capacitor is required across VPP and ground to suppress spurious voltage transients.
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15. DC Programming Characteristics
TA = 25 5C, VCC = 6.5 0.25V, VPP = 13.0 0.25V
Limits Symbol ILI VIL VIH VOL VOH ICC2 IPP2 VID Parameter Input Load Current Input Low Level Input High Level Output Low Voltage Output High Voltage VCC Supply Current (Program and Verify) VPP Supply Current A9 Product Identification Voltage CE = VIL 11.5 IOL = 2.1 mA IOH = -400 A 2.4 40 20 12.5 Test Conditions VIN = VIL, VIH -0.6 2.0 Min Max 10 0.8 VCC + 0.7 0.4 Units A V V V V mA mA V
16. AC Programming Characteristics
TA = 25 5C, VCC = 6.5 0.25V, VPP = 13.0 0.25V
Limits Symbol tAS tOES tDS tAH tDH tDFP tVPS tVCS tPW tOE tPRT Notes: Parameter Address Setup Time OE Setup Time Data Setup Time Address Hold Time Data Hold Time OE High to Output Float Delay VPP Setup Time VCC Setup Time CE Program Pulse Width(3) Data Valid from OE(2) VPP Pulse Rise Time During Programming
(2)
Test Conditions(1)
Min 2 2
Max
Units s s s s s
Input Rise and Fall Times: (10% to 90%) 20 ns Input Pulse Levels: 0.45V to 2.4V
2 0 2 0 130
ns s s
Input Timing Reference Level: 0.8V to 2.0V Output Timing Reference Level: 0.8V to 2.0V
2 2 95 105 150 50
s ns ns
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven - see timing diagram. 3. Program Pulse width tolerance is 100 sec 5%.
17. Atmel's AT27C040 Integrated Product Identification Code
Pins Codes Manufacturer Device Type A0 0 1 O7 0 0 O6 0 0 O5 0 0 O4 1 0 O3 1 1 O2 1 0 O1 1 1 O0 0 1 Hex Data 1E 0B
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AT27C040
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AT27C040
18. Rapid Programming Algorithm
A 100 s CE pulse width is used to program. The address is set to the first location. VCC is raised to 6.5V and VPP is raised to 13.0V. Each address is first programmed with one 100 s CE pulse without verification. Then a verification/reprogramming loop is executed for each address. In the event a byte fails to pass verification, up to 10 successive 100 s pulses are applied with a verification after each pulse. If the byte fails to verify after 10 pulses have been applied, the part is considered failed. After the byte verifies properly, the next address is selected until all have been checked. VPP is then lowered to 5.0V and VCC to 5.0V. All bytes are read again and compared with the original data to determine if the device passes or fails.
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19. Ordering Information
19.1 Standard Package
ICC (mA) tACC (ns) 70 Active 30 Standby 0.1 Ordering Code AT27C040-70JI AT27C040-70PI AT27C040-70TI AT27C040-90JI AT27C040-90PI AT27C040-90TI Package 32J 32P6 32T 32J 32P6 32T Operation Range Industrial (-40 C to 85 C) Industrial (-40 C to 85 C)
90
30
0.1
Note:
Not recommended for new designs. Use Green package option.
19.2
Green Package Option (Pb/Halide-free)
ICC (mA) Active 30 Standby 0.1 Ordering Code AT27C040-70JU AT27C040-70PU AT27C040-70TU AT27C040-90JU AT27C040-90PU AT27C040-90TU Package 32J 32P6 32T 32J 32P6 32T Operation Range Industrial (-40 C to 85 C) Industrial (-40 C to 85 C)
tACC (ns) 70
90
30
0.1
Package Type 32J 32P6 32T 32-lead, Plastic J-leaded Chip Carrier (PLCC) 32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 32-lead, Plastic Thin Small Outline Package (TSOP)
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AT27C040
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AT27C040
20. Package Information
20.1 32J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075)
E1 B
E
B1
E2
e D1 D A A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL
D2
MIN 3.175 1.524 0.381 12.319 11.354 9.906 14.859 13.894 12.471 0.660 0.330
NOM - - - - - - - - - - - 1.270 TYP
MAX 3.556 2.413 - 12.573 11.506 10.922 15.113 14.046 13.487 0.813 0.533
NOTE
A A1 A2 D D1 D2
Note 2
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum.
E E1 E2 B B1 e
Note 2
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 32J REV. B
R
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20.2
32P6 - PDIP
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eB
0 ~ 15
REF
SYMBOL A A1 D E E1 B
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 41.783 15.240 13.462 0.356 1.041 3.048 0.203 15.494 NOM - - - - - - - - - - 2.540 TYP MAX 4.826 - 42.291 15.875 13.970 0.559 1.651 3.556 0.381 17.526 Note 1 Note 1 NOTE
Note:
1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
B1 L C eB e
09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 32P6 REV. B
R
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AT27C040
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AT27C040
20.3 32T - TSOP
PIN 1
0 ~ 8
c
Pin 1 Identifier D1 D
L
e
b
L1
E
A2
A
SEATING PLANE
GAGE PLANE
A1
SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.05 0.95 19.80 18.30 7.90 0.50 NOM - - 1.00 20.00 18.40 8.00 0.60 0.25 BASIC 0.17 0.10 0.22 - 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 20.20 18.50 8.10 0.70 Note 2 Note 2 NOTE
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 32T REV. B
R
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